instruction execution

英 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]

美 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]

网络  指令执行

计算机

英英释义

noun

• (computer science) the process of carrying out an instruction by a computer
  Synonym:execution

双语例句

• When complete, the original instruction is executed ( from the breakpoint), and execution continues at that point.
  执行完成之后，接着执行原始的指令（从断点开始）。
• A technique whereby the receiver fetches the next instruction before completing execution of the previous instruction, in order to increase processing speed.
  在前一条指令全部执行完之前就开始取下一条指令，以提高处理速度的一种技术。
• Characteristics of the microprocessor are fast speed and nimble instructions. The way of raising speed is to adopt pipelining in instruction execution.
  它的运算速度提高的途径是指令的执行采用流水线方式，指令缓冲部件IB采用两个体交替接收指令和执行指令的办法来减少取指令的等待时间。
• The Digital Signal Processing which is regarded as CPU on board has some advantages, such as fast instruction execution, high bus bandwidth, and high speed real-time data processing.
  数据采集卡部分使用使用DSP来作采集卡CPU具有指令执行速度快、总线带宽高、可以完成数据的高速实时处理等优点。
• Traditional programming model like C, C++ and Fortran are poorly suited to multi-core architectures because of the assumed single instruction stream execution model and centralized memory structure.
  C、C++和Fortran等基于单指令流和统一存储结构的传统编程模型已经无法适应多核处理器结构。
• Compile the assembler into machine code so that generate PLE file in order to implement the execution mechanism of PLC virtual machine. In this way, the instruction execution speed of PLC is greatly increased and we can save much memory.
  用汇编编译器编译转变成功的汇编程序产生机器码，从而构造出可执行文件&PLE文件，实现PLC虚拟机的机器码执行机制，这样大大提高了PLC指令的执行速度，同时大大节约了内存空间。
• In the traditional Cache, the Cache hit ratio is insured only by the address locality of memory reference instruction stream during program execution, it restricts the improvement of Cache hit ratio.
  在传统的Cache中，仅仅依靠程序执行时访存指令流地址的局域性来保证较高的Cache命中率，使得Cache命中率的提高受到限制。
• Static instruction scheduling decides the execution order of instructions and improves the instruction-level parallelism by reducing stall caused by dependences.
  静态指令调度决定指令执行顺序，屏蔽指令间由于依赖关系而产生的延迟，从而提高了指令的并行度。
• In the instruction execution pipeline stage, scalable pipeline technology was adopted to realize the video processing instruction.
  为有效实现扩展指令，处理器执行级采用了可扩展流水级技术。
• Research and Analysis of the Value Prediction and Instruction Reuse Techniques in Speculated Execution
  推测执行中值预测与指令重用技术的研究与分析